M_STOP_DET=ENABLED, M_RD_REQ=ENABLED, M_TX_OVER=ENABLED, M_RX_OVER=ENABLED, M_RX_DONE=ENABLED, M_RX_UNDER=ENABLED, M_RESTART_DET=ENABLED, M_MASTER_ON_HOLD_READ_ONLY=ENABLED, M_RX_FULL=ENABLED, M_TX_EMPTY=ENABLED, M_TX_ABRT=ENABLED, M_START_DET=ENABLED, M_ACTIVITY=ENABLED, M_GEN_CALL=ENABLED
I2C Interrupt Mask Register.
These bits mask their corresponding interrupt status bits. This register is active low; a value of 0 masks the interrupt, whereas a value of 1 unmasks the interrupt.
| M_RX_UNDER | This bit masks the R_RX_UNDER interrupt in IC_INTR_STAT register. Reset value: 0x1 0 (ENABLED): RX_UNDER interrupt is masked 1 (DISABLED): RX_UNDER interrupt is unmasked |
| M_RX_OVER | This bit masks the R_RX_OVER interrupt in IC_INTR_STAT register. Reset value: 0x1 0 (ENABLED): RX_OVER interrupt is masked 1 (DISABLED): RX_OVER interrupt is unmasked |
| M_RX_FULL | This bit masks the R_RX_FULL interrupt in IC_INTR_STAT register. Reset value: 0x1 0 (ENABLED): RX_FULL interrupt is masked 1 (DISABLED): RX_FULL interrupt is unmasked |
| M_TX_OVER | This bit masks the R_TX_OVER interrupt in IC_INTR_STAT register. Reset value: 0x1 0 (ENABLED): TX_OVER interrupt is masked 1 (DISABLED): TX_OVER interrupt is unmasked |
| M_TX_EMPTY | This bit masks the R_TX_EMPTY interrupt in IC_INTR_STAT register. Reset value: 0x1 0 (ENABLED): TX_EMPTY interrupt is masked 1 (DISABLED): TX_EMPTY interrupt is unmasked |
| M_RD_REQ | This bit masks the R_RD_REQ interrupt in IC_INTR_STAT register. Reset value: 0x1 0 (ENABLED): RD_REQ interrupt is masked 1 (DISABLED): RD_REQ interrupt is unmasked |
| M_TX_ABRT | This bit masks the R_TX_ABRT interrupt in IC_INTR_STAT register. Reset value: 0x1 0 (ENABLED): TX_ABORT interrupt is masked 1 (DISABLED): TX_ABORT interrupt is unmasked |
| M_RX_DONE | This bit masks the R_RX_DONE interrupt in IC_INTR_STAT register. Reset value: 0x1 0 (ENABLED): RX_DONE interrupt is masked 1 (DISABLED): RX_DONE interrupt is unmasked |
| M_ACTIVITY | This bit masks the R_ACTIVITY interrupt in IC_INTR_STAT register. Reset value: 0x0 0 (ENABLED): ACTIVITY interrupt is masked 1 (DISABLED): ACTIVITY interrupt is unmasked |
| M_STOP_DET | This bit masks the R_STOP_DET interrupt in IC_INTR_STAT register. Reset value: 0x0 0 (ENABLED): STOP_DET interrupt is masked 1 (DISABLED): STOP_DET interrupt is unmasked |
| M_START_DET | This bit masks the R_START_DET interrupt in IC_INTR_STAT register. Reset value: 0x0 0 (ENABLED): START_DET interrupt is masked 1 (DISABLED): START_DET interrupt is unmasked |
| M_GEN_CALL | This bit masks the R_GEN_CALL interrupt in IC_INTR_STAT register. Reset value: 0x1 0 (ENABLED): GEN_CALL interrupt is masked 1 (DISABLED): GEN_CALL interrupt is unmasked |
| M_RESTART_DET | This bit masks the R_RESTART_DET interrupt in IC_INTR_STAT register. Reset value: 0x0 0 (ENABLED): RESTART_DET interrupt is masked 1 (DISABLED): RESTART_DET interrupt is unmasked |
| M_MASTER_ON_HOLD_READ_ONLY | This M_MASTER_ON_HOLD_read_only bit masks the R_MASTER_ON_HOLD interrupt in IC_INTR_STAT register. Reset value: 0x0 0 (ENABLED): MASTER_ON_HOLD interrupt is masked 1 (DISABLED): MASTER_ON_HOLD interrupt is unmasked |